1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. More particularly, the invention relates to a semiconductor device having a superjunction structure and a method for manufacturing the semiconductor device.
2. Description of the Related Art
Vertical power MOSFETs have been proposed as higher breakdown voltage metal-oxide semiconductor field-effect transistors (MOSFETs) Important characteristics of this type of higher breakdown voltage MOSFETs include lower ON resistance and higher breakdown voltage performance. ON resistance and breakdown voltage depend on the resistivity of a electric field relaxing layer and are in a tradeoff relation to each other in such a manner that ON resistance can be lowered by raising the impurity concentration in the electric field relaxing layer, thereby lowering the resistivity, whereas breakdown voltage decreases simultaneously.
In recent years, as a technique for lowering ON resistance while maintaining breakdown voltage performance in higher breakdown voltage MOSFETs, superjunction structures have been proposed.
FIG. 1 is a sectional view that shows the construction of unit structure in an active element region in a related art semiconductor device having such a superjunction structure.
A semiconductor device 1 includes a semiconductor body 2, an n-type drift region 3 that is formed on the semiconductor body 2 and functions as an electric field relaxing layer, a base region 4 formed on the n-type drift region 3, a source region 5 formed in the base region 4, a gate insulating film 6, a gate electrode 7 formed on the gate insulating film 6, an insulating film 8 formed on the gate electrode 7, a source electrode 9 that is formed on the insulating film 8 and is connected to the source region 5, a p-type column region 10 formed between two gate electrodes 7 that are adjacent to each other in the n-type drift region 3, and a drain electrode 11 formed on a rear surface of the semiconductor body 2. In an actual semiconductor device, this unit structure is cyclically formed in a transverse direction in the figure.
The semiconductor body 2, the n-type drift region 3 and the source region 5 are of the same conductivity type (an n-type here). The base region 4 and the p-type column region 10 are of a conductivity type reverse to that of the n-type drift region 3 (a p-type here). Furthermore, in the n-type drift region 3 and the p-type column region 10, the impurity dose amounts of these regions are set substantially equal.
Next, the operation of the semiconductor device having a construction as described above. When a reverse-bias voltage is applied to between the drain and the source in a case where a bias voltage is not applied to between the gate and the source (the MOSFET is off), a depletion layer expands from two pn junctions of the base region 4 and the n-type drift region 3 and of the p-type column region 10 and the n-type drift region 3 and a leakage current between the drain and source is suppressed. That is, because an interface between the p-type column region 10 and the n-type drift region 3 extends in a longitudinal direction between the drain and the source, the depletion layer widens in a transverse direction from this interface. When the region of the distance d shown in FIG. 1 becomes depleted, the depletion layers that expands from the each pn junction of the n-type column region 10 and the n-type drift region 3 are coupled.
Therefore, when the p-type column region 10 and the n-type drift region 3 are regulated so that the distance d becomes sufficiently small, the breakdown voltage of the semiconductor device 1 does not depend anymore on the impurity concentration of the n-type drift region 3 that functions as an electric field relaxing layer. For this reason, by adopting a superjunction structure as described above, it becomes possible to maintain breakdown voltage performance while raising the impurity concentration of the n-type drift region 3, thereby lowering ON resistance.
Japanese Patent Laid-Open No. 2001-135819 (a corresponding U.S. patent application number is U.S. Pat. No. 6,512,268 B1) discloses a semiconductor element having the above-described superjunction structure, although this is an example of a planar-type gate electrode MOSFET.
In a semiconductor element having a superjunction structure, a higher breakdown voltage is applied to the cell region as described above, and therefore it becomes important to ensure breakdown voltage at a junction-terminal region in a peripheral region that is formed at the periphery of an active element region. As a technique for applying higher breakdown voltage to a junction-terminal region, Japanese Patent Laid-Open No. 2003-273355 (a corresponding U.S. patent application number is US 2003/0222327 A1) discloses a construction of a semiconductor element which is such that in a planar-type gate electrode MOSFET having a superjunction structure, an n-type drift region and a p-type drift region are formed not only in a cell region, but also in the vicinity of a peripheral edge of a junction-terminal region.
A p-type base layer is formed on a p-type drift region in the vicinity of an interface with a cell region portion in the junction-terminal region. An insulating film is formed on a surface of the junction-terminal region, with the exception of part of this p-type base layer, and a field electrode is formed on this insulating film so as to surround the cell region portion. The field electrode comes into contact with a surface of the p-type base layer and is electrically connected to a source electrode. By adopting this structure, abrupt changes on the equipotential surface in the junction-terminal region are suppressed. As a consequence, in this structure, the field electrode is formed on the p-type drift region in the vicinity of the interface with the cell region portion in the junction-terminal region.
Takaya et al., “Floating Island and Thick Bottom Oxide Trench Gate MOSFET (FITMOS)”, Proceedings of the 17th International Symposium on Power Semiconductor Devices & ICS, May 23-26, 2005, pp. 43-46 (hereinafter referred to as “Takaya et al.”) and Japanese Patent Laid-Open No. 2006-32420 disclose a semiconductor device which is such that a thick oxide film, an n-type drift region and a reverse conduction type (p-type) region are provided below a trench-type gate electrode of vertical MOSFET formed in a cell region. It is claimed that thanks to this construction, higher breakdown voltage designs become possible and ON resistance characteristics are improved. And it is described that a thick oxide film and a reverse conduction type region can be provided below a gate electrode formed not only in a cell region, but also in a pn junction terminal portion. As a result of this, it is claimed that it is possible to prevent an increase in the number of steps.
By setting the pitch between the column regions at a narrow value so that the whole of the p-type column region 10 and the n-type drift region 3 becomes depleted, the dependence of breakdown voltage on the impurity concentration of the n-type drift region 3 is suppressed and it becomes possible to raise the superjunction effect. Particularly, in a device having a low resistance (for example, on the order of not more than 100 V) between the drain and the source, it is desirable to form a fine superjunction structure. However, the present inventor recognized that there is a difficulty as described below. Even in a case where the pitch between the p-type columns regions 10 is set at a narrow value, when a step in which the material is subjected to high temperatures is performed thereafter, an impurity in the p-type column region 10 diffuses into the n-type drift region 3 and the p-type column region 10 widens in a transverse direction, with the result that it becomes difficult to narrow the pitch. For this reason, in a semiconductor device having a fine superjunction structure, it is necessary to examine a manufacturing process which is such that the number of heat cycles applied to the semiconductor device is reduced after the formation of the p-type column region 10.
As a procedure for manufacturing a semiconductor element which is such that as disclosed in Japanese Patent Laid-Open No. 2003-273355, an n-type drift layer (an n-type drift region) and a p-type drift layer (a p-type column region) are formed also in a junction-terminal region and a field electrode is formed also thereon, the following methods are available:    (1) After the formation of a p-type column region by ion implantation, a field electrode is formed on the column region.    (2) After the formation of a field electrode, ion implantation is performed from above the electrode and a p-type column region is formed.
As described above, in a semiconductor device having a fine superjunction structure, it is desirable that the number of heat cycles applied to the semiconductor device be as small as possible after the formation of the p-type column. Ordinarily the field electrode of the semiconductor element is formed by the growth of a polysilicon layer by the CVD (Chemical Vapor Deposition) method, the temperature of the semiconductor device becomes high during formation. For this reason, in the method (1) above, an impurity in the p-type column region diffuses into the n-type drift region during the formation of the field electrode and it becomes difficult to realize a fine superjunction structure.
On the other hand, in the method (2) above, it becomes possible to reduce the number of heat cycles, because the p-type column region is formed after the formation of the field electrode. FIG. 2 is a sectional view that shows the construction of an prototype semiconductor device in which after the formation of a field electrode, ion implantation is performed from above the electrode by the method (2) above and a p-type column region is formed.
A semiconductor device 12 includes a semiconductor body 13, an n-type drift region 14 that is formed on the semiconductor body 13 and functions as an electric field relaxing layer, a base region 15 formed on the n-type drift region 14, a source region 16 formed in the base region 15, a gate insulating film, a gate electrode 17 formed on the gate insulating film (and a connecting electrode 17a connected to the gate electrode 17), an insulating film 18 formed on the gate electrode 17, a source electrode 19 that is formed on the insulating film 18 and connected to the source region 16, a p-type column region 20 (and 20a) formed between two gate electrodes 17 that are adjacent to each other in the n-type drift region 14, a drain electrode 21 formed on a rear surface of the semiconductor body 13, and an element isolating region 22. The semiconductor device 12 has an active element region in which the gate electrode 17 is formed and a peripheral region formed at the periphery of the active element region. The semiconductor device 12 further includes a field electrode 23 formed on the semiconductor body 13 in the peripheral region. The field electrode 23 is electrically connected to the gate electrode 17 via the connecting electrode 17a formed in the peripheral region. The field electrode 23 is formed on almost the whole surface of the peripheral region in order to obtain a contact to the connecting electrode 17a. 
The p-type column region 20 is formed by the ion implantation of a p-type impurity by using a mask having an opening of a prescribed pattern on the semiconductor body 13. In this construction, the method (2) above is used. Therefore, in the peripheral region, ion implantation is performed via the field electrode 23 that has already been formed. For this reason, the depth of the p-type column region 20a present in the peripheral region is smaller than the depth of the p-type column region 20 of the active element region. Because the above-described superjunction effect depends on the depth of a p-type column region, and the deeper the p-type column region, the greater the effect will be. Therefore, when a p-type column region in a peripheral region is formed in a shallow position, the breakdown voltage of the peripheral region becomes lower than the breakdown voltage of an active element region. As a result of this, the breakdown voltage of the whole semiconductor device 12 is determined by the breakdown voltage of the peripheral region. That is, even when an element in an active element region is manufactured by controlling various conditions in order to achieve a higher breakdown voltage, it becomes difficult to improve the breakdown voltage of the whole semiconductor device 12. From this point of view, it is necessary to manufacture a semiconductor device so that a withstand voltage higher than in an active element region can be maintained in a peripheral region.
In a vertical MOSFET element having a superjunction structure, by connecting a trench-type gate electrode formed in an active element region to a field electrode formed in a peripheral region of the active element region, it becomes possible to control the gate potential via the field electrode. For this reason, it is necessary that a connection point to the trench-type gate electrode be provided at least in one place on the peripheral region side outward from a pn junction terminal portion. From this necessity, a gate electrode that is not related to cell operations is formed in a peripheral region. Electric field intensity becomes apt to be increased under the gate electrode and this causes a deterioration in breakdown voltage.
Furthermore, the present inventor found out that in a construction which is such that a thick oxide film, an n-type drift region and a reverse conduction type (p-type) region are provided under a trench-type gate electrode, as disclosed in Takaya et al. and Japanese Patent Laid-Open No. 2006-32420, it is possible to reduce the electric field intensity under the gate electrode, whereas there arises the problem that in the cell region an increase in resistance and an increase in gate capacitance are caused.